Runlength Compression Techniques for FPGA Configurations

The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that can significantly reduce this overhead. By using runlength and other compression techniques, files can be compressed by a factor of 3.6 times. Bus transfer mechanisms and decompression hardware are also discussed. This results in a single compression methodology which achieves higher compression ratios than existing algorithms in an off-line version, as well as a somewhat lower quality compression approach which is suitable for on-line use in dynamic circuit generation and other mapping-time critical situations. CONFIGURATION COMPRESSION Reconfigurable computing is an exciting new area that harnesses the programmable power of FPGAs. In the past, FPGAs were used in applications that required them to be configured only once or a few times. The infrequency in which the FPGAs were programmed meant that these applications were not limited by the device's slow configuration time [1]. However, as reconfigurable computing is becoming more popular, the configuration overhead is becoming a true burden to the useful computation time. For example, applications on the DISC and DISC II systems have spent 25% [6] to 71% [5] of their execution time performing reconfiguration. Reconfigurable computing demands an efficient configuration method. In order for reconfigurable computing to be effective, there must be a method to quickly configure the device with a minimal amount of data transfer. However, the amount of information needed to configure an entire FPGA can be quite large. Sending this large amount of information to the FPGA can be quite time consuming, in addition to power consuming. A logical solution would be to compress the data stream sent to the FPGA. This would reduce the amount of external storage needed to hold the configuration, reduce the amount of time needed to send the configuration information to the device, and reduce the amount of communication through the power-hungry off-chip I/O of the FPGA. Once the configuration information arrives to the decompression hardware in the FPGA, it can be written to the configuration memory at a faster rate than would have been possible through the slow I/O of the device. In previous work [2, 3] we developed a technique using the wildcard feature of the Xilinx XC6200 series FPGA [7]. While this algorithm provided good compression results, it also requires a very complex compression algorithm, and may not achieve the best possible compression results. In this paper we explore the configuration information of the Xilinx XC6200 series. Based on the nature of the data, several compression techniques will be proposed. Using these compression techniques, algorithms and support hardware structures are developed to compress the address/data pairs sent to the device. Next, these compression strategies are performed on a group of Xilinx XC6216 configurations to determine their performance. Finally, conclusions will be drawn on the capabilities of these techniques. CONFIGURATION INFORMATION The Xilinx XC6200 FPGA is an SRAM based, high performance Sea-Of-Gates FPGA optimized for reconfigurable computing. All configuration resources are accessed by addressing the SRAM through a standard memory interface. The Xilinx XC6200 series are partially reconfigurable devices. The configuration file consists of a set of address/data pairs. Since the device is partially reconfigurable, the target addresses written to may not be contiguous. Therefore, if the data is compressed the addresses must be compressed as well. The configuration data falls into four major areas: cell function, routing, input/output buffers, and control. The addresses which configure the cell function, routing, and the input/output buffers will normally never be written to more than once in a configuration. The control data may be written to multiple times in a configuration, but this data represents a very small fraction of the total configuration. In addition, the addresses that are accessed usually fall in